1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device having stacked gates.
2. Description of the Prior Art
With the progress of technology, wireless communication has been developed rapidly and become the major form of communicating information in modern society. The wireless communication is performed between equipment having analog/radio frequency (RF) devices used for data converting, transmitting, receiving or amplifying, etc. The performances of the analog/RF devices therefore have significant influences on the transmitting speed and accuracy of the wireless communication.
However, the electrical characteristics of the analog/RF devices such as on-current (Ion)/transconductance (Gm), on-resistance (Ron), parasitic capacitance and breakdown voltage (BVD) usually have contrary trends. For example, in the process of performance optimization, attempts have been made to form analog/RF devices having parallel-connected gates in order to boost the on-current, but the parasitic capacitance is adversely increased. On the other hand, devices having serially-connected gates are proposed in order to reduce the parasitic capacitance, but the on-resistance is adversely increased.
In light of the above, there is still a need in the field to provide a device of which an optimized balance between these electrical characteristics aforesaid may be obtained and therefore an overall better performance may be achieved.